1. Field of the Invention
The present invention generally relates to buffer circuitry and, more particularly, to a tag buffer integrated circuit with testing capabilities.
2. Description of the Related Art
A buffer is a circuit device which is basically a synchronizing element between two different forms of other circuit devices. A tag buffer is a special type of buffer used in an electrical system architecture to store informative "tags." Tags are used to give an indication to the overall system as to where data or instructions are located.
A tag buffer includes several components: a storage device, such as a random access memory (RAM), generally having address, data and control signal inputs and outputs; a comparator circuit; a parity generator; and a parity checker or detector. FIG. 1 indicates a typical tag buffer system architecture, e.g., as commercially available in the Am10469/100469 parts manufactured by Advanced Micro Devices, Inc., Sunnyvale, Calif.
A common use for a tag buffer is in an integrated circuit memory system. A typical system is shown in FIG. 2. As depicted, a computer system may have both a main memory and a cache memory. The cache memory is a small but very fast supplementary computer memory between the main memory and the central processing unit (CPU). The system is generally designed to use the cache to give the effect of a larger and faster main memory. The cache memory is transparent to the user whose program need not address the cache. The cache is generally controlled to be loaded with the addressed word plus words from adjacent memory locations. Since programs are usually sequential in nature, such a block of words is very likely to be entirely in the cache. In this manner, often-used data or instructions can be in the cache, relieving the CPU from constantly having to access the main memory. Hence, operations can be performed much faster.
Tag buffers are used both in address translation cache and data cache applications. The key function of a tag buffer is to compare the internal data bits of a memory with external data bits. An equality of the internal and external data is then confirmed or denied by an output signal from the tag buffer.
Referring to FIG. 1, a tag buffer might have nine internal data bits and one output bit. For example, address tags are stored in the tag buffer storage device. The external data, viz., a tag word on inputs D, are compared to the internal data. Each tag word is composed of eight bits of data and one bit of parity (in practice, the word can be expanded to any desired width). An output of a digital logic HIGH (MISS signal) from the comparator component could be used to indicate that the word sought by the CPU is not in the cache; similarly, an output of a digital logic LOW (MATCH or HIT signal) could be used to indicate the word is in the cache. Parity is generated internally (eliminating system parity generation). During a COMPARE cycle, the eight bits of data are monitored for odd parity by the parity checker.
It is difficult to test the functionality and switching characteristics of a device such as the tag buffer which includes a multi-bit storage component because its content cannot be read out through the input/output pins. Therefore, a tag buffer which includes a designed-in method for testing and built-in test facilities is needed.